1. Field of the Invention
The present invention relates to a logic synthesis device for LSI circuit using CAD technology and a logic synthesis method therefor, and particularly relates to a logic synthesis device for LSI circuit with hierarchical design and a logic synthesis method therefor.
2. Description of the Related Art
With recent advance in integration technology, LSI circuits have been becoming larger and more complicated, which results in complicated design work for logic circuits. Under such circumstances, hierarchical designing has been adopted to facilitate the design of complicated configuration in LSI circuit. In this designing method, an LSI circuit is treated as modules and divided into a plurality of blocks or a plurality of functional blocks for designing purpose. Besides, CAD (Computer Aided Design) technology is used for logic synthesis of LSI circuit. Various logic synthesis devices for logic synthesis have been proposed.
Examples of such logic synthesis device for LSI circuit with hierarchical design include a logic synthesis device which makes logic synthesis of the entire LSI at a time without any block division of LSI and a logic synthesis device which divides an LSI into blocks and makes logic synthesis inside each of the blocks, which are disclosed in Japanese Patent Application Laid-open No. 84676/1991 and No. 116281/1991 respectively. However, these patents do not disclose any logic synthesis method for the blocks constituting the LSI.
In the logic synthesis program used in such conventional logic synthesis devices, the wire length between blocks constituting the LSI cannot be automatically estimated. The LSI circuit designer must input all data related to the wires between the blocks to the logic synthesis program or insert some data for the wires of the part with severe requirements from the viewpoint of circuit operation alone and provide them to the logic synthesis program for logic synthesis between the blocks.
In an LSI with hierarchical design, however, many wires over blocks constituting the LSI are often complicatedly routed and, if the data related to wiring between the blocks are manually input to the logic synthesis program, omission or error in wire specification and critical paths easily occur. It is necessary to repeat logic synthesis until all omissions and errors in wire specification and critical paths are cleaned. Thus, logic synthesis with conventional logic synthesis device as above requires many operators and many manhours as well as long designing period.